Not applicable.
1. Field of the Invention
The present invention relates generally to computer graphics and, more particularly to synchronized rendering and display of images across multiple display devices.
2. Background Art
Obtaining visual realism is crucial in computer graphics systems. To this end, it is often necessary to produce multiple levels of images on a single display device (e.g., a CRT, LCD, active matrix or plasma display). In the alternative, some graphics systems seek to achieve visual reality by generating a large visual image across multiple display devices. Flight simulation applications are an example where multiple display devices are used. Each display contributes to the overall image by providing either a front, left, or right view of the scene. As the simulated flight progresses, each of the front, left, and right views change. Proper synchronization between the various display devices is key to maintaining the reality of the scene being presented.
Load balancing is another application that requires synchronization. Parts of a scene are separately generated and then blended together.
Synchronization is made difficult, however, by the varying complexities of the images being presented on the various displays. As a result, many graphics systems will become desynchronized and produce visual artifacts or distortions in the resulting image. Previous attempts to prevent the occurrence of these distortions have been directed to hardware solutions at the graphics pipeline level. However, these solutions are expensive to implement.
What is needed is a solution that will work with off-the-shelf (i.e., commercially available) hardware.
The present invention provides a graphics system and method for performing synchronized image display and swap buffering in a multiple display/multiple processor environment. Synchronization is achieved through a master-slave dichotomy.
The graphics system has a master system and a plurality of slave systems. Each slave system contributes to the generation of a common scene. One or more processors are included within each slave system. One processor is made responsible for controlling the functions of each slave system with respect to synchronization. Each slave system also has I/O ports to provide communications between it and the master system. A plurality of daughter cards are included within each slave system. Each daughter card is an integrated circuit board used for timing synchronization between the slave systems and the master system.
The slave systems further include a plurality of graphics processors (i.e., graphics accelerators or coprocessors). Finally, each slave system has a device driver. The device driver is responsible for receiving and processing commands to the graphics processors. In addition, the device driver performs time synchronization with the master system and executes commands transmitted from the master.
The master system synchronizes the rendering and display functions of the slave systems. Like the slave systems, the master system also includes one or more processors and I/O ports. In addition, the master system has a synchronization signal generator. The synchronization signal generator is used to provide a timing signal to each daughter card located within the slave systems.
The graphics system further includes a multidrop cable. The multidrop cable provides communications between the slave systems and the master system. The multidrop cable is designed such that any transmission communicated over it will arrive at the I/O ports of the slave systems at approximately the same time. In further embodiments, communications between the slave systems and the master system is provided using a daisy chain wiring scheme.
The present invention addresses synchronization of vertical retrace and buffer swapping. In one embodiment, synchronization of image display and vertical retrace is achieved through transmission of a clock signal generated by the synchronization signal generator in the master system and provided in a daisy chain manner to the daughter cards located within the slave systems.
In another embodiment, synchronization of vertical retrace is achieved through a clocking means available through performance counters or processor clocks. In still another embodiment, synchronization is used to manage buffer swapping among the multiple processors so that rendering is synchronized.